Advanced Silicon-Germanium-Epitaxy
The incorporation of Germanium into the Silicon lattice enables the usage of the industrial proved strained Silicon technology. Stretching the Silicon lattice gains the benefit of local enhanced carrier mobility for CMOS devices or provides the capability of producing Hetero-Bipolar-Transistors (HBT) for high frequency applications.
The Epi process is designed for a multi layer stack containing a strained SixGe1-x layer (HBT base) doped with Boron and Carbon and a top Si layer doped with Arsenic (HBT emitter). The Carbon content ensures a significantly reduced Boron diffusion out of the base region to get a superior HBT performance.
The SiGe:C Epi process performed within the temperature range of 600 ? 750°C is exceptionally stable and very well monitored by high-resolution XRD metrology.
Parameter
| Wafer size | 6 inch wafers |
| Epi stack | Si / SixGe1-x / Si |
| Wafer surface | Blanket Silicon or patterned Oxide |
| Thickness SiGe | 20 ? 50 nm |
| Thickness Si | 10 ? 100 nm |
| Thickness uniformity | +/- 3% |
| Dopant | Boron, Arsenic, Carbon |
For further information, please contact our FOUNDRY Team at info(at)telefunkensemi.com

